Problems synthesis device clock synchronization receivers satellite telecommunication data transmission systems
DOI:
https://doi.org/10.20535/RADAP.2014.58.55-66Keywords:
clock synchronization, steady state error variance, discriminatory responseAbstract
The paper presents mathematical models to formalize an analytical description of receivers clocked devices of satellite telecommunication transmit systems. The principles of synchronization synthesis in view of the negative factors by minimizing their influence on signal processing are shown. A broadening theoretical interpretation of the analytical description for the operation and optimization of receiver parameters in a real and complex interference effects on signal processing system manipulated by examining changes in the density distribution of errors regarding synchronization of clock synchronization.
It is proposed to optimize clocked devices by providing them like standalone device and evaluate the quality of the accuracy degree of the fluctuation variance errors.
It is shown that the use of this approach allows for structural synthesis device clock to search device structure that pro vides the maximum value assigned to the criterion of efficiency.
References
Перелік посилань
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