Studying of the Fletcher algorithm and developing VHDL model of hashing device
DOI:
https://doi.org/10.20535/RADAP.2023.94.64-69Keywords:
Fletcher, VHDL, HDL, hashing, checksum, model, hardware modelling, Adler, design, hashAbstract
The relevance of hardware modelling of the Fletcher algorithm is related to its widespread use for control of document and image authentication, data transfer between components of various systems, and the advantages provided by hardware implementation over software. Compared to a software-based approach, hardware modelling can improve data processing efficiency by optimising computations at the hardware level. This leads to a significant reduction in the execution time of, so there is a need for a detailed study of the characteristics of this algorithm.
The article presents the stages of development of an information hashing device based on the Fletcher-64 algorithm in the Active-HDL environment. The VHDL hardware description language is used to implement the model. The device is tested and its design features are considered. A description of the interface part of the device with the size of the data buses, a description of the object architecture, and a simulation of the developed VHDL model of Fletcher-64 are given. The Fletcher-64 VHDL model processes information in 32-bit blocks in one cycle. The value of the hash sum is stored in the OUT_DATA bus in hex format.
A comparative characterisation of Fletcher with the Adler-32 algorithm is carried out. It is determined that Fletcher-32 and Fletcher-64 provide better bit shuffling, while Fletcher-16 is inferior to Adler-32 in error detection and bit shuffling. It is determined that the use of Fletcher-32 for data integrity control is more efficient than the Adler-32 algorithm due to better error detection. The feasibility of using different versions of Fletcher for incoming messages of variable length, taking into account the peculiarities of the alphabet, is assessed.
As a result of the work, the ways of further research aimed at finding collisions for the Fletcher, Adler, CRC algorithms are identified; the acceptable areas of use of Fletcher and Adler-32 are determined.
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