FPGA Implementation of Viterbi Decoder for Satellite System

Authors

  • M. P. Pavlenko National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev
  • V. E. Bychkov National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev
  • V. I. Pravda National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev

DOI:

https://doi.org/10.20535/RADAP.2012.49.71-76

Keywords:

FPGA, Forward Error Correction, decoder Viterbi, trellis diagram

Abstract

Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. This paper presents a short overview of a Viterbi decoder FPGA (Field-Programmable Gate Array) implementation for Thuraya wireless communication sys-tem in Verilog HDL (Hardware Description Language). The main goal of this project was re-source-optimized implementation of the decoder on the target platform. In this project, Viterbi Decoder is implemented on Altera Cyclone III FPGA. The transmitter is of constraint length 5 and of rate 1/4. The Viterbi decoder can operate at a frequency of 90 MHz.

Author Biographies

M. P. Pavlenko, National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev

Павленко М.П., магістрант радіотехнічного факультету

V. E. Bychkov, National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev

Бичков В.Є., асист. кафедри радіотехнічних пристроїв та систем

V. I. Pravda, National Technical University of Ukraine, Kyiv Politechnic Institute, Kiev

Cand. of Sc. (Tech), Prof.

References

Бернард Скляр. Цифровая связь. М., Вильямс,2007

Дж. Кларк, мл., Дж. Кейн. Кодирование с исправлением ошибок в системах цифровой связи. М. : Радио и связь, 1987

Стешенко В.Б., Петров А.В. Апаратнная реализация декодера Витерби

Hema. S, Suresh Babu. V., Ramesh P. FPGA Implementation of Viterbi Decoder.

Milos Pilipovic, Marija Tadic. FPGA Implementation of Soft Input Viterbi Decoder for CDMA2000 System.

Behzad Momahed Heravi, Bahram Honary. Multi-rate Parameterized Viterbi Decoding for Partial Reconfiguration.

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Published

2012-01-27

How to Cite

Павленко, М., Бичков, В. and Правда, В. (2012) “FPGA Implementation of Viterbi Decoder for Satellite System”, Visnyk NTUU KPI Seriia - Radiotekhnika Radioaparatobuduvannia, 0(49), pp. 71-76. doi: 10.20535/RADAP.2012.49.71-76.

Issue

No. 49 (2012)

Section

Theory and Telecommunications Facilities

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