Temperature stability of ultra low voltage signals multiplier
DOI:
https://doi.org/10.20535/RADAP.2017.69.49-55Keywords:
signals multiplier, temperature stability, integrated chip correlators, vektor signals multiplying, signals samplesAbstract
The paper considers the thermal stability of ultra low voltage signals multipliers that form the basis of discrete-analog programmable filter-correlators. These correlators perform convolution vector of the input signal samples and a sequence of weighting coefficients impulse function. These coefficients take two values: +1 or -1. The multiplier is based on a MOS transistor. The first factor appears voltage signal sampling, which is stored on the gate of the transistor, and the second is determined by the location where the current of the transistor will be sent, which is the result of multiplying. In this case, the weighting factor is one that will be sent to the current summing bus "positive" current, and the pulse rate function determines -1 multiplier connection summing bus "negative" current. The final result of multiplication of vectors is generated by subtracting the output signals weighted summation of tires. Alternatively this conversion can be output currents to two outer transducers voltage differential signal current and formation voltage as an output voltage. Since the MOSFET current is subject to temperature dependence, this factor affects the accuracy of multiplication. Analysis of this relationship and the possibility of its weakening presented in this paper. In particular, the strategy of linear and non-linear approximation to the thermostable point is proposed. An analytical relationship is obtained for the necessary conditions for temperature stabilization. For the non-linear approximation strategy, a circuit with a nonlinear element-a bipolar transistor-is proposed. Experimental results of improving the temperature stabilization for both strategies are obtained.References
Перечень ссылок
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References
Nandini A.S., Madhavan S. and Sharma Ch. (2012) Design and Implementation of Analog Multiplier with Improwed Linearity, International Journal of VLSI design & Communication Systems (VLSICS), Vol.3, No.5 pp. 93-109. DOI: 10.5121/vlsic.2012.3508
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