FPGA Implementation of Viterbi Decoder for Satellite System
Keywords:FPGA, Forward Error Correction, decoder Viterbi, trellis diagram
Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. This paper presents a short overview of a Viterbi decoder FPGA (Field-Programmable Gate Array) implementation for Thuraya wireless communication sys-tem in Verilog HDL (Hardware Description Language). The main goal of this project was re-source-optimized implementation of the decoder on the target platform. In this project, Viterbi Decoder is implemented on Altera Cyclone III FPGA. The transmitter is of constraint length 5 and of rate 1/4. The Viterbi decoder can operate at a frequency of 90 MHz.
Бернард Скляр. Цифровая связь. М., Вильямс,2007
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Стешенко В.Б., Петров А.В. Апаратнная реализация декодера Витерби
Hema. S, Suresh Babu. V., Ramesh P. FPGA Implementation of Viterbi Decoder.
Milos Pilipovic, Marija Tadic. FPGA Implementation of Soft Input Viterbi Decoder for CDMA2000 System.
Behzad Momahed Heravi, Bahram Honary. Multi-rate Parameterized Viterbi Decoding for Partial Reconfiguration.
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